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%   BibTeX entry for \cite{brp:1991c}
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%   Copyright (c) 2004 by Bruno R. Preiss, P.Eng.
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%   URL:http://www.brpreiss.com/papers/published/1991/ccece/paper.bib
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%   Copyright (c) 1999 by Bruno R. Preiss, P.Eng.
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%   $Author: brpreiss $
%   $Date: 2001/12/09 19:22:40 $
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@string{ablex = "Ablex Publishing Corporation"}
@string{acm = "Association for Computing Machinery, Inc."}
@string{acmsurveys = "ACM Computing Surveys"}
@string{acmtomacs = "ACM Trans.\ on Modeling and Computer Simulation"}
@string{acmtoplas = "ACM Trans.\ on Programming Languages and Systems"}
@string{ass = " Ann.\ Simulation Symp."}
@string{brp = "Bruno R. Preiss"}
@string{cacm = "Communications of the ACM"}
@string{ccece = " Canadian Conf.\ on Elec.\ and Comp.\ Eng."}
@string{ccng = "Computer Communications Networks Group"}
@string{ccvlsi = " Canadian Conf.\ on VLSI"}
@string{cips = "Canadian Information Processing Society"}
@string{csece = "Canadian Society for Electrical and Computer Engineering"}
@string{ece = "Department of Electrical and Computer Engineering"}
@string{ee = "Department of Electrical Engineering"}
@string{eic = "Engineering Institute of Canada"}
@string{home = "http://www.brpreiss.com"}
@string{icpp = " Int.\ Conf.\ on Parallel Processing"}
@string{ieee = "Institute of Electrical and Electronics Engineers, Inc."}
@string{ieeecomp = "IEEE Computer"}
@string{ieeemicro = "IEEE Micro"}
@string{ieeetc = "IEEE Trans.\ on Computers"}
@string{ieeetcad = "IEEE Trans.\ on Computer-Aided Design"}
@string{ieeetpds = "IEEE Trans.\ on Parallel and Distributed Systems"}
@string{ieeetse = "IEEE Trans.\ on Software Engineering"}
@string{ijcs = "International Journal in Computer Simulation"}
@string{infocom = " INFOCOM"}
@string{isca = " Int.\ Symp.\ on Computer Architecture"}
@string{jpdc = "Journal of Parallel and Distributed Computing"}
@string{pads = " Workshop on Parallel and Distributed Simulation"}
@string{pennstate = "Pennsylvania State University"}
@string{proc = "Proc.\ "}
@string{sc = "Simulation Councils, Inc."}
@string{scs = "Society for Computer Simulation"}
@string{scsmcds = " SCS Multiconf. on Distributed Simulation"}
@string{tscs = "Trans.\ of the Society for Computer Simulation"}
@string{ut = "University of Toronto"}
@string{uw = "University of Waterloo"}
@string{wiley = "John Wiley \& Sons"}
@string{wsc = " Winter Simulation Conf."}

%
%   Copyright (c) 1999, 2000 by Bruno R. Preiss, P.Eng.
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%   $Author: brpreiss $
%   $Date: 2004/11/13 13:48:41 $
%   $RCSfile: preiss.bib,v $
%   $Revision: 1.204 $
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%   $Id: preiss.bib,v 1.204 2004/11/13 13:48:41 brpreiss Exp $
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@inproceedings{brp:1991c,
    url = home # "/papers/published/1991/ccece/paper.pdf",
    bibtex = home # "/papers/published/1991/ccece/paper.bib",
    author = "Ian Donald Mac{I}ntyre and Bruno Richard Preiss",
    title = "Multi-Threaded Pipelining in a {RISC} Processor",
    booktitle = proc # 1991 # ccece,
    address = "Qu\'ebec, P.Q.",
    organization = csece,
    month = Sep,
    year = 1991,
    pages = "7.3.1--7.3.6",
    copyright = eic,
    abstract =
    {
	This paper examines the effects of multithreaded pipelining
	on the CPI (cycles per instruction) of a RISC processor.
	The desired CPI in a conventional (single-threaded) RISC processor
	is one instruction per cycle.
	However, the CPI is typically more than one
	because of data hazards, control hazards,
	and resource hazards in the pipeline.
	\par
	A multi-threaded processor performs a context switch
	between every instruction.
	Multi-threaded pipelining
	holds out the promise of achieving a lower CPI
	because it can eliminate data and control hazards,
	and mask the effects of memory latency.
	However, multi-threaded pipelining reduces cache hit ratios
	and requires more chip area to implement.
	\par
	In this paper, we present a model for predicting
	the CPI of a multi-threaded pipelined processor.
	We also present the results of trace-driven simulations
	of single- and multi-threaded processors.
	These data show that, for reasonable implementation technologies,
	and taking into account the chip area penalty,
	a multi-threaded processor can achieve a lower
	CPI than a single-threaded processor.
    }
}