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%   BibTeX entry for \cite{brp:1984a}
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%   Copyright (c) 2004 by Bruno R. Preiss, P.Eng.
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%   URL:http://www.brpreiss.com/theses/masc/thesis.bib
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%   Copyright (c) 1999 by Bruno R. Preiss, P.Eng.
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%   $Author: brpreiss $
%   $Date: 2001/12/09 19:22:40 $
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@string{ablex = "Ablex Publishing Corporation"}
@string{acm = "Association for Computing Machinery, Inc."}
@string{acmsurveys = "ACM Computing Surveys"}
@string{acmtomacs = "ACM Trans.\ on Modeling and Computer Simulation"}
@string{acmtoplas = "ACM Trans.\ on Programming Languages and Systems"}
@string{ass = " Ann.\ Simulation Symp."}
@string{brp = "Bruno R. Preiss"}
@string{cacm = "Communications of the ACM"}
@string{ccece = " Canadian Conf.\ on Elec.\ and Comp.\ Eng."}
@string{ccng = "Computer Communications Networks Group"}
@string{ccvlsi = " Canadian Conf.\ on VLSI"}
@string{cips = "Canadian Information Processing Society"}
@string{csece = "Canadian Society for Electrical and Computer Engineering"}
@string{ece = "Department of Electrical and Computer Engineering"}
@string{ee = "Department of Electrical Engineering"}
@string{eic = "Engineering Institute of Canada"}
@string{home = "http://www.brpreiss.com"}
@string{icpp = " Int.\ Conf.\ on Parallel Processing"}
@string{ieee = "Institute of Electrical and Electronics Engineers, Inc."}
@string{ieeecomp = "IEEE Computer"}
@string{ieeemicro = "IEEE Micro"}
@string{ieeetc = "IEEE Trans.\ on Computers"}
@string{ieeetcad = "IEEE Trans.\ on Computer-Aided Design"}
@string{ieeetpds = "IEEE Trans.\ on Parallel and Distributed Systems"}
@string{ieeetse = "IEEE Trans.\ on Software Engineering"}
@string{ijcs = "International Journal in Computer Simulation"}
@string{infocom = " INFOCOM"}
@string{isca = " Int.\ Symp.\ on Computer Architecture"}
@string{jpdc = "Journal of Parallel and Distributed Computing"}
@string{pads = " Workshop on Parallel and Distributed Simulation"}
@string{pennstate = "Pennsylvania State University"}
@string{proc = "Proc.\ "}
@string{sc = "Simulation Councils, Inc."}
@string{scs = "Society for Computer Simulation"}
@string{scsmcds = " SCS Multiconf. on Distributed Simulation"}
@string{tscs = "Trans.\ of the Society for Computer Simulation"}
@string{ut = "University of Toronto"}
@string{uw = "University of Waterloo"}
@string{wiley = "John Wiley \& Sons"}
@string{wsc = " Winter Simulation Conf."}

%
%   Copyright (c) 1999, 2000 by Bruno R. Preiss, P.Eng.
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%   $Author: brpreiss $
%   $Date: 2004/11/13 13:48:41 $
%   $RCSfile: preiss.bib,v $
%   $Revision: 1.204 $
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%   $Id: preiss.bib,v 1.204 2004/11/13 13:48:41 brpreiss Exp $
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@mastersthesis{brp:1984a,
    url = home # "/theses/masc/thesis.pdf",
    bibtex = home # "/theses/masc/thesis.bib",
    catalogue = "http://library.utoronto.ca:8002/MARION?ind=c\&key=theses\%20ELENG\%201984\%20M.A.Sc.\%200785",
    author = "Bruno Richard Preiss",
    title = "Design and Simulation of a Data-Flow Multiprocessor",
    school = ee # ", " # ut,
    year = 1984,
    note = "157~pp.",
    copyright = brp,
    abstract =
    {
	A data-flow execution model that supports program reentrancy, recursion
	and automatic run-time loop unraveling without the use of tagged tokens
	is described.
	This execution model is based on a novel data-flow program graph
	representation scheme which is a hybrid of static and dynamic data-flow
	program representation methods.
	In particular, the use of separate instruction and data token spaces
	allows program reentrancy.
	Execution environments called contexts execute acyclic data-flow graphs
	associated with high-level code blocks.
	Iteration and function calling are implemented by the dynamic creation
	of contexts.
	\par
	A multiprocessor architecture that supports this execution model is
	proposed.
	The system architecture is based on a partitioned ring in which each
	partition of the ring is a conventional processor/memory bus.
	Each processor consists of a processing element and a task manager
	together with a portion of global memory.
	\par
	The proposed architecture has been simulated in software.
	A number of test programs have been developed and their execution
	on the proposed architecture has been evaluated.
	The performance of the proposed architecture with various numbers of
	processing elements is described.
	In addition, a number of task scheduling algorithms are presented
	and evaluated.
    }
}